1. Field of the Invention
The present invention relates to a method of fabricating nanowires, to a method of fabricating an electronic device based on semiconductor nanowires obtained by the method, and to a transistor based on semiconductor nanowires likewise obtained by the method.
2. Description of the Related Art
More particularly, the invention relates to a method of fabricating silicon nanowires by plasma enhanced chemical vapor deposition (PECVD) and by thermal annealing, i.e. a method that is “dry”, as opposed to methods that use a liquid. The method of the invention makes it possible to fabricate nanowires in which morphological properties such as shape (straight or rolled up), size, and/or length are under control.
The invention also relates to the use of such silicon nanowires in micro- and nano-electronic applications, e.g. for making transistors and connectors.
It has been known for a few years how to fabricate ordered structures of very small sizes such as carbon nanotubes, silicon nanowires, and silicon nanosticks.
For example, document FR 2 860 780 (D. Pribat et al.) describes a method of fabricating carbon nanowires from a nanoporous matrix in which a metal catalyst is deposited. The carbon nanowires grow epitaxially perpendicularly to the surface of the crystalline substrate.
Document FR 2 888 041 (D. Pribat et al.) also describes fabricating silicon nanowires or nanosticks using a vapor-liquid-solid (VLS) method. In that method, hollow pores are etched in an aluminum substrate, a metallic catalyst is deposited at the bottom of the pores, and then silicon nanowires are grown, which nanowires may be selectively doped during growth so as to generate conductor wires or electronic junctions of the negative intrinsic negative (NIN) or positive intrinsic positive (PIP) type. Once more, the nanowires likewise grow perpendicularly to the surface of the substrate. Solutions for using such nanowires consist in making the nanowires grow transversely to a surface and then in transferring them to another substrate so as to position them, e.g. between two electrical contacts formed on the surface of the sample.
Nanotubes and nanowires present electrical characteristics that are particularly advantageous, given that their conductivity may be several orders of magnitude greater than the conductivity of structures of micrometer or sub-micrometer size.
The nanowires obtained with the techniques described in those prior documents grow perpendicularly to the surface on which the catalyst is deposited. In order to obtain wires parallel to the surface of the substrate it is therefore necessary to form pores parallel to said surface and to deposit the catalyst at the bottom of the pores (cf. FR 2 888 041).
Nevertheless, VLS methods are complicated since they require a plurality of steps and a plurality of different techniques. A method generally takes place by implementing the following steps: 1) cleaning the substrate; 2) depositing catalyst, e.g. by evaporation; 3) annealing the evaporated layer in an oven in order to form droplets; 4) transferring the substrate with the catalysts to a chemical vapor deposition (CVD) chamber; and 5) growing nanowires by exposing the catalyst to a gas, e.g. silane, at a temperature higher than the melting temperature of the drops of catalyst. Some of those steps require high temperatures (T>600° C.). In addition, all of those operations and the sample transfers between the various steps must be performed in a clean room in order to avoid contamination by dust of micrometer or nanometer size. Furthermore, the catalyst is at least partially oxidized on being exposed to air.
Those VLS methods are generally lengthy and expensive and may give rise to problems of reproducibility, given the large number of steps and techniques involved. In addition, those methods lead to growth that is vertical (transverse to the surface of the substrate), which is not very favourable to the use of nanowires for forming electrical connections. The only example of horizontal growth of nanowires that is described in the D. Pribat patents is based on the use of specific porous matrices of Al2O3.
Furthermore, methods of depositing and etching thin layers are known that involve plasma enhanced chemical vapor deposition (PECVD) for use in fabricating microelectronic components, flat screens, and solar cells.
Plasma methods have the advantage of being performed in vacuum chamber at controlled temperature and pressure, of being rapid, and of enabling very good uniformity to be obtained over very large areas. It is also possible to control the crystallographic structure of the deposited layers as a function of conditions concerning the composition of the gases making up the plasma, pressure, and temperature, . . . . It is thus known how to deposit layers of silicon in the amorphous, polycrystalline, microcrystalline, or nanocrystalline, . . . state. These layers may subsequently be etched selectively using known photolithographic methods of masking and exposure for fabricating sub-micrometric structures. Nevertheless, photolithography is limited by the optical limit of diffraction, and it is difficult to fabricate structures set by nanometric dimensions using those techniques.